Design & Reuse
63 IP
51
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 40LP/LL
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption. For usage with either hosts, dev...
52
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USB 2.0 PHY IP, Silicon Proven in TSMC 55LP
In order to deliver great performance and use little power, the whole physical layer (PHY) IP solution for USB 2.0 was developed. The High-Speed USB 2...
53
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 65LP
A complete physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP. The USB2.0 IP imp...
54
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 7FF
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed USB 2.0 tra...
55
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USB 2.0 PHY IP, Silicon Proven in TSMC 90G
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed USB 2.0 tra...
56
0.0
USB 2.0 PHY IP, Silicon Proven in UMC 28HPC
The USB 2.0 PHY IP Core offers a complete physical layer (PHY) solution for high performance and low power. It implements a High-Speed USB 2.0 transce...
57
0.0
USB 2.0 PHY IP, Silicon Proven in UMC 40LP
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for excellent performance and low power consumption. The High-Speed USB 2.0 trans...
58
0.0
USB 2.0 PHY IP, Silicon Proven in UMC 55SP/EF
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed USB 2.0...
59
0.0
USB 2.0/1.1 PHY (6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
USB 2.0 PHY M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power consumptio...
60
0.0
USB2.0 Full-Speed Transceiver
The Renesas USB2.0 FS(Full-Speed) Transceiver is useful analog 1port transceiver hard macro for TSMC 22nm ULL process. This macro can be configured to...
61
0.0
eUSB 2.0 PHY in TSMC (N3A) for Automotive
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
62
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eUSB2V2 PHY in TSMC (22nm)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
63
0.0
Type-C PHY
Innosilicon Type-C IP is composed of the physical layer and the PHY logic. The physical layer contains 4 data channels, an AUX channel and bias circui...